Quick links

Talk

Reinventing the Internet

Date and Time
Friday, October 5, 2018 - 3:00pm to 4:30pm
Location
McDonnell Hall A01
Type
Talk

Reinventing the Internet

Presenter:
Jennifer Rexford ’91, Gordon Y.S. Wu Professor of Engineering, Professor of Computer Science and Computer Science Department Chair

This event is part of She Roars: Celebrating Women at Princeton

Trading Networks

Date and Time
Tuesday, October 9, 2018 - 12:30pm to 1:30pm
Location
Computer Science Small Auditorium (Room 105)
Type
Talk
Speaker
Andy Myers ’96, from Jane Street
Host
Jennifer Rexford & David Walker

Andy Myers
This talk will discuss some of the unique ways in which trading firms use (and misuse) various bits of technology (switches, layer-1 devices, microwaves, FPGAs), to build networking infrastructure that achieves their goals.

Bio:
Andy Myers has been building low latency trading systems at Jane Street since 2014. Previously he was a Systems Architect at GETCO.  He received his A.B. from Princeton in 1996 and his MS from Carnegie Mellon in 1998.

Lunch will be served to talk attendees at 12:00pm.

High-performance Graph Processing on GPUs

Date and Time
Friday, October 12, 2018 - 12:30pm to 1:30pm
Location
Computer Science Small Auditorium (Room 105)
Type
Talk
Host
Margaret Martonosi

Back in 2013, implementing high-performance graph algorithms for GPUs required manual coding in CUDA, a slow and difficult process.  To significantly lower the level of effort required, we created IrGL, a language and compiler specifically for generating high-performance graph algorithm implementations for GPUs. Powered by three throughput optimizations, the IrGL-generated code outperformed nearly all handwritten graph algorithms achieving speedups of up to 6x.

Freed from the drudgery of writing low-level code, IrGL has allowed us to look at a number of problems revolving around graphs. We've used the high-performance implementations to identify key memory system bottlenecks that limit performance on current GPU architectures.
We've also translated graph database queries to IrGL and executed them on GPUs. In the course of extending this to the general problem of subgraph isomorphism (a key primitive in graph databases), we were named GraphChallenge 2017 champions for our implementation of the triangle-counting and k-truss problems.

Along the way, we also built Groute, a runtime for asynchronous multi-GPU graph analytics that has achieved order-of-magnitude improvements over existing synchronous implementations. We sped up exhaustive testing of software by traversing graphs that were too big to materialize in memory.  Recently, we have also used IrGL's ability to generate hundreds of variants of the same graph algorithm to explore correctness and performance portability issues on GPUs.

Many interesting questions still remain unexplored, however, and I will summarize our current efforts in this area.

[Joint work with Keshav Pingali, Tal Ben-Nun, Michael Sutton, M. Amber Hassaan, Chad Voegele, Yi-Shan Lu, Ahmet Celik, Milos Gligoric, Sarfraz Khurshid, Tyler Sorensen and Alastair Donaldson]

Bio:
Sreepathi Pai is an Assistant Professor of Computer Science at the University of Rochester. His research interests are in compilers, programming languages and implementation, performance models and computer architecture. His most recent research has revolved around the IrGL compiler that produces high-performance GPU code for graph algorithms.

He earned his PhD at the Indian Institute of Science and his B.E. in Computer Engineering at the University of Mumbai. Prior to joining the Department of Computer Science at Rochester, he was a Postdoctoral Fellow at the University of Texas at Austin.

Panel Discussion on Transformations in Engineering and the Arts

Date and Time
Friday, June 1, 2018 - 10:00am to 11:30am
Location
Lewis Library 120
Type
Talk

Panel Discussion on Transformations in Engineering and the Arts, a Course Open to All Students

Panelists: 
-Naomi Ehrich Leonard ’85, Professor of Mechanical and Aerospace Engineering, and Director, Council on Science and Technology
-Sigrid M. Adriaenssens, Associate Professor of Civil and Environmental Engineering
-Aatish Bhatia, Associate Director, Engineering Education; Council on Science and Technology
-Jane Cox, Senior Lecturer and Director, Theater
-Adam Finkelstein, Professor of Computer Science
-Jeff Snyder, Senior Lecturer of Music

This event is part of Princeton University's Reunion 2018 celebration

Changing the Game: A Different Approach to Cybersecurity

Date and Time
Thursday, April 19, 2018 - 4:30pm to 6:00pm
Location
Robertson Hall, Arthur Lewis Auditorium
Type
Talk
Speaker
J. Michael Daniel 92, from Cyberthreat Alliance

OPEN TO THE PUBLIC

Mr. Daniel's keynote address launches the policy conference, Cyber Security and Warfare in the 21st Century, co-sponsored by the Center for International Security Studies and the Center for Information Technology Policy. The conference will take place on April 20 from 8:45am-5:00pm in Arthur Lewis Auditorium.  Please register here

Michael Daniel currently serves as the President of the Cyber Threat Alliance (CTA). CTA works to improve the cybersecurity of our global digital ecosystem by enabling real-time, high-quality cyber threat information sharing among companies and organizations in the cybersecurity field. Prior to joining the CTA in February 2017, Michael served from June 2012 to January 2017 as Special Assistant to President Obama and Cybersecurity Coordinator on the National Security Council Staff. In this role, Michael led the development of national cybersecurity strategy and policy, and ensured that the US government effectively partnered with the private sector, non-governmental organizations, and other nations.

Speaker(s): 
J. Michael Daniel, President, Cyberthreat Alliance
Former Special Assistant to President Obama and White House Cybersecurity Coordinator

Network-Centric Computing for Online Services

Date and Time
Monday, March 12, 2018 - 4:30pm to 6:00pm
Location
Engineering Quadrangle B205
Type
Talk
Speaker

Modern datacenters offer an abundance of online services to billions of daily users. The most demanding online services come with tight response latency requirements, forcing service providers to keep their massive datasets memory-resident, distributed across the datacenter’s servers. Every user request accesses the memory of hundreds of servers; therefore, fast access to the aggregate memory pool is of crucial importance for service quality. The entity binding all the memory resources together is the datacenter network. Unfortunately, despite the dramatic evolution of datacenter fabrics over the past decade, networking still incurs a latency overhead of tens of microseconds to every remote memory access, making memory pooling impractical. In this talk, I will propose a holistic network-centric system redesign to enable memory pooling in future datacenters, which includes (i) a specialized lightweight network stack; (ii) on-chip integration of the network interface logic; and (iii) new network operations with richer, end-to-end semantics. I will highlight the role and demonstrate the effect of each of these three key features with systems built throughout my dissertation.

Bio:
Alexandros (Alex) Daglis is a sixth-year PhD student at EPFL, advised by Prof. Babak Falsafi and Prof. Edouard Bugnion. His research interests lie in rack-scale computing and datacenter architectures. Alex advocates tighter integration and co-design of network and compute resources as a necessary approach to tackling the performance overheads associated with inter-node communication in scale-out architectures. He has been a founding member of Scale-Out NUMA, an architecture, programming model, and communication protocol for low-latency, distributed in-memory processing. Scale-Out NUMA has been prototyped and awarded a US patent. As an intern at HP Labs, Alex worked on the design of The Machine’s unique memory subsystem. More details can be found on his CV.

The Rise of Artificial Intelligence: Who Will Have Jobs in the Future?

Date and Time
Thursday, March 1, 2018 - 4:30pm to 6:00pm
Location
McCosh Hall 50
Type
Talk

A conversation with Brad Smith, President and Chief Legal Officer of Microsoft.
 

Please register here: Eventbrite
 
Info about the new book from Microsoft, The Future Computed: Artificial Intelligence and its role in society
 
Brad Smith’s bio and photos

Women's Interactive Networking Event (WINE)

Date and Time
Wednesday, November 15, 2017 - 4:30pm to 6:00pm
Location
Computer Science Tea Room
Type
Talk
Host
Marshini Chetty

At this meeting, we will have a short talk by Margaret Martonosi, Professor of CS at Princeton followed by small group discussions to share personal experiences of success and failure at creating change to advance diversity. We will then join together for a large group discussion to share key insights and brainstorm topics for future WINE meetings. 

Open to graduate students, post docs and faculty of all genders!

Global Measurements of Internet Censorship

Date and Time
Friday, April 14, 2017 - 12:30pm to 1:30pm
Location
127 Corwin Hall
Type
Talk
Host
The Program for Quantitative and Analytical Political Science, Department of Politics

Photo of Professor Nick Feamster

Photo by David Kelly Crow

Internet users in many countries around the world are subject to various forms of censorship and information control. Despite its widespread nature, however, measuring Internet censorship on a global scale has remained an elusive goal. Internet censorship is known to vary across time and within regions (and Internet Service Providers) within a country. To capture these complex dynamics, Internet censorship measurement must be both continuous and distributed across a large number of vantage points.  To date, gathering such information has required recruiting volunteers to perform measurements from within countries of interest; this approach does not permit collection of continuous measurements, and it also does not permit collection from a large number of measurement locations; it may also put the people performing the measurements at risk. Over the past four years, we have developed a collection of measurement techniques to surmount the limitations of these conventional approaches. In this talk, I will describe three such techniques: (1) Encore, a tool that performs cross-origin requests to measure Web filtering; (2) Augur, a tool that exploits side-channel information in the Internet Protocol (IP) to measure filtering using network-level access control lists; and (3) a tool to measure DNS filtering using queries through open DNS resolvers. These three tools allow us—for the first time ever—to characterize Internet censorship continuously, from hundreds of countries around the world, at different layers of the network protocol stack. each of these techniques involves both technical and ethical challenges. I will describe some of the challenges that we faced in designing and implementing these tools, how we tackled these challenges, our experiences with measurements to date, and our plans for the future. Long term, our goal is to collaborate with social scientists to bring data to bear on a wide variety of questions concerning Internet censorship and information control; I will conclude with an appeal to cross-disciplinary work in this area and some ideas for how computer scientists and social scientists might work together on some of these pressing questions going forward.

This research is in collaboration with Sam Burnett, Roya Ensafi, Paul Pearce, Ben Jones, Frank Li, and Vern Paxson.

Interrupts in OS code: let’s reason about them. Yes, this means concurrency.

Date and Time
Monday, May 16, 2016 - 11:00am to 12:00pm
Location
Computer Science 402
Type
Talk
Speaker

Existing modelled and verified operating systems (OS’s) typically run on uniprocessor platforms and run with interrupts mostly disabled. This makes formal reasoning more tractable: execution is mostly sequential. The eChronos OS is a real-time OS used in tightly constrained devices, running on (uniprocessor) embedded micro-controllers. It is used in the DARPA-funded HACMS program, where it runs the flight control software of a high-assurance quadcopter. To provide low latency, the eChronos OS runs with interrupts enabled and provides a preemptive scheduler. In terms of verification, this means that concurrency reasoning is required, which significantly increases the complexity: application and OS instructions may be interleaved with interrupt handler instructions.

In our work we explicitly model the effect of interrupts and their handling by the hardware and OS. We provide a general formal model of the interleaving between OS code, application code and interrupt handlers. We then instantiate this model to formalise the scheduling behavior of the eChronos OS, and prove the main scheduler property: the running task is always the highest-priority runnable task.

June Andronick is a Senior Researcher at Data61|CSIRO (formerly NICTA). Her research focuses on increasing the reliability of critical software systems, by mathematically proving that the code behaves as expected and satisfies security and safety requirements.  She contributed to the seL4 correctness proof and now focuses on concurrency reasoning for OS code. She leads the concurrency software verification research in Data61, and is deputy leader of the Trustworthy Systems group. She was recognised in 2011 by MIT's Technology Review as one of the world's top young innovators (TR35). She holds a PhD in Computer Science from the University of Paris-Sud, France.

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