Design of the PRAM Network
The Princeton University PRAM computer network provides process-to-process data transmission rates equivalent to memory access rates with negligible latency penalties and currently costs less than 1,000.00 dollars per gigabit of network bandwidth. The PRAM network architecture described in this report scales
to 10,000 node computer networks using fast optical technology. The cost of such a PRAM network implementation is expected, in the near term, to fall to $100.00 per gigabit of network bandwidth. Princeton University has been running a prototype hetrogeneous wide area PRAM network since early 1988. The system includes Apple Macintosh IIs, IBM PC/ATs and Clones, and Sun Series 3 workstations running Mac OS, DOS, OS/2, Xenix, Sun OS, and Mach. We have 6 PLAN boards (4x4 optical switches designed and fabricated at Princeton University) cascaded together to provide a single 14-way PRAM shared memory. The longest run of fiber in the network is one kilometer, however, the current prototype
will support fiber runs up to three kilometers without repeaters. We have produced over 100 PRAM interface cards for the ISA, Nu, and VME buses as well as prototype PRAM-Capture networked data acquisition cards. All the prototype boards use inexpensive off-the-shelf parts for the bus interface, memory, and dual memory port arbitration. All fiber optic duplex serial ports are implemented with 125 MHz Advanced Micro Devices Taxi chips clocked at 6MHz in the 9-bit mode. The electrical to optical conversion is performed through 850 nm ODLs manufactured by Sumitomo Electric and Hewlett-Packard.