05-04

Nicholas Richardson FPO

Nicholas Richardson will present his FPO "Gradient-based Optimization of Geometry with Application to Optical Computing" on Monday, May 4, 2026 at 11:00 AM in CS 401.

The members of Nicholas’s committee are as follows:
Examiners: Ryan Adams (Adviser) Margaret Martonosi, Benjamin Eysenbach,
Readers: Szymon Rusinkiewicz, Elif Ertekin (UIUC)

A copy of his thesis is available upon request.  Please email gradinfo@cs.princeton.edu if you would like a copy of the thesis.

Everyone is invited to attend the talk.

Abstract follows below:
The automated design of engineered systems — reducing human expertise to a specification and delegating search to computation — is one of the central ambitions of computational science and optimization.

In this thesis, I present work at the intersection of optimization techniques and their application to inverse design of computational hardware. First, I present a novel method, Fiber Monte Carlo, which enables gradient-based optimization in optimization problems containing parametric discontinuities; this is a class of problems that arise in a wide variety of applications, including graphics, topology optimization, computational geometry, and physical simulation.

Next, I turn to the computational design of electromagnetic systems. I first detail the development of a custom differentiable electromagnetic field solver, JaxEM, with native support for inverse design applications. The construction of this simulator enables straightforward gradient-based design of structured hardware.

Finally, I apply Fiber Monte Carlo and JaxEM to the inverse design of specialized hardware for an optical classifier. This chapter contains a standalone contribution by way of a novel method to achieve nonlinear computation using only linear optics. The hardware is designed in silico using Fiber Monte Carlo based topology optimization, and we use gradient methods by differentiating through simulations performed with JaxEM. The resulting design was fabricated as a silicon photonic chip, providing an end-to-end demonstration of gradient-based automated hardware design in physical silicon.