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Architectural Techniques to Efficiently Handle Big Data Challenges

Date and Time
Thursday, January 18, 2018 - 11:00am to 12:00pm
Computer Science Small Auditorium (Room 105)
CS Department Colloquium Series
Margaret Martonosi, Electrical Engineering

Natalie Enright Jerger
As Moore’s Law continues in the post-Dennard scaling era, architects and programmers must consider energy efficiency even more carefully as part of their designs. The energy cost of moving and storing data exceeds that of computing with that data. At the same time, we expect to see 100s of zettabytes of digital data in the next decade.  This explosion of data that must be analyzes creates numerous challenges for current designs. In this talk, we will look at two techniques to address big data challenges facing computer architecture.  One promising approach to boost both energy efficiency and performance is approximate computing. The approximate computing paradigm trades-off correctness for improvements in energy and/or performance by targeting key applications that do not require 100% accurate execution such as image processing and machine learning.  We propose a microarchitectural technique, load value approximation that selectively predicts memory values in order to forego expensive accesses to the memory hierarchy. By predicting instead of moving data, we can save energy and improve the performance when a small amount of error is tolerable. In the second part of my talk, I will discuss the performance-cost trade-offs of interposer-based multi-chip, multi-core systems. Connecting multiple disparate chips via a silicon interposer allows us to tightly couple processors and memory within the same package for efficient data movement. I will briefly present our network solutions to realize these systems.  Considering solutions that span technology, architecture and software opens up new opportunities to solve energy and performance challenges facing next generation systems. 

Natalie Enright Jerger is the Percy Edward Hart Professor of Electrical and Computer Engineering  at the University of Toronto. Prior to joining the University of Toronto, she received her MSEE and PhD from the University of Wisconsin-Madison in 2004 and 2008, respectively. She received her Bachelor's degree from Purdue University in 2002. She is a recipient of the Ontario Ministry of Research and Innovation Early Researcher Award in 2012, the 2014 Ontario Professional Engineers Young Engineer Medal recipient and the 2015 Borg Early Career Award winner. She served as the program co-chair of the 7th Network-on-Chip Symposium and as the program chair of the 20th International Symposium on High Performance Computer Architecture. She is currently serving as the ACM SIGMICRO Vice Chair and an ACM SIGARCH Executive Committee member.  Her current research explores on-chip networks, approximate computing, IoT architectures and machine learning acceleration. She is also passionate about increasing the representation of women in computing, particular in computer architecture.  She currently chairs the organizing committee for the Women in Computer Architecture group (WICARCH). In 2017, she co-authored the second edition of the Computer Architecture Synthesis Lecture on On-Chip Networks with Li-Shiuan Peh and Tushar Krishna. Her research is supported by NSERC, Intel, CFI, AMD, Huawei and Qualcomm.

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