Marcelo Orenes Vera

Computer Science PhD Candidate

Princeton University


I am a fourth-year graduate student in Computer Science at Princeton University advised by Professor Margaret Martonosi and Professor David Wentzlaff. My broad area of research within Computer Architecture is accelerating memory-bottlenecked applications via modular hardware, and developing Formal Verification methodologies for it. I work within the DECADES project, a full-stack system design that aims to improve the performance, power and programmability of several emerging workflows in the broad areas of Machine Learning and Graph Analytics..

Before joining Graduate School I worked at Arm for 2 years, where I contibuted to the development of the Mali GPU’s G76, G77 and G78. I worked there as a Hardware Engineer taking responsability on Formal Verification and hardware design of the Texture Cache subsystem.

Prior working at Arm I mainly focused on application software. I worked with Professor Mercedes Valdes Vela at Murcia University, where I received my bachelors degree in Computer Science. My research involved creating an indoor location system based on Bluetooth 4.0 LE technology to guide users in museums with the help of a mobile App, to after analyse the patterns of user trajectories inside the building. We leverage techniques like Clustering to profile users based on their movement behaviour and App interaction. We personalized the user experience based on the profile detected by the ML algorithm. This project led to a startup, which won the 3rd prize on the regional YUZZ Young Entrepreneurs contest in 2016 and 2nd prize on the Murcia University Startup creation contest in 2017.

Outside work, I enjoy playing soccer, rock climbing, cycling and doing cross-country ski during the winter.

Please feel free to read more about me on my CV, available for download in this page, together with the link to my GitHub.


  • Computer Architecture
  • Heterogeneous parallelism
  • Software-defined hardware and domain-specific architectures
  • Hardware Design


  • PhD in Computer Architecture, Current

    Princeton University

  • BSc in Computer Science, 2017

    University of Murcia (Spain)

  • Exchange year Computer Science, 2016

    University of Hasselt (Belgium)



A DARPA-funded project to create specialized, reconfigurable hardware to accelerate important applications.


Tiny but Mighty: Designing and Realizing Scalable Latency Tolerance for Manycore SoCs

In the 49th Annual International Symposium on Computer Architecture (ISCA '22)

AutoSVA: Democratizing Formal Verification of RTL Module Interactions

In the 58th ACM/IEEE Design Automation Conference (DAC 21)

MosaicSim: A Lightweight, Modular Simulator for Heterogeneous Systems

In The International Symposium on Performance Analysis of Systems and Software (ISPASS), 2020
Nominated for Best Paper Award



PhD candidate

Princeton University

Sep 2019 – Present Princeton, New Jersey
  • Designing full-stack approaches to optimize the performance, power, and programmability of graph and other sparse analytics that are the heart of many modern big data applications; contributing to the development of a specialized, reconfigurable hardware platform for accelerating different software applications as part of DARPA’s Software Defined Hardware (SDH) program

Hardware engineer

Arm Ltd.

Jul 2017 – Aug 2019 Trondheim, Norway
  • Investigation and design of optimizations to the current implementation of several modules within the Texture Mapper of the Mali GPU, specifically the Texture Cache and the miss-path of it. Multilevel cache systems development and replacement policies optimization for performance and bandwidth saving. I also worked in the main pipeline of data access in an out of order execution architecture.
  • Formal Verification at Unit Level and Bug hunting approaches for liveness properties between units. UVM usage for simulation testbench of the texturing unit.

Undergraduate Research Assistant

University of Murcia

Feb 2016 – Jul 2017 Murcia, Spain
  • Developing a platform for indoor location based on Bluetooth 4.0 LE technology and analysis of user trajectories making use of clustering techniques.