Abstractions for Programming the Data Plane at Line Rate

The evolution of network switches has been driven primarily by performance. Recently, thanks in part to the emergence of large datacenter networks, the need for better control over network operations, and the desire for new features, programmability of switches has become as important as performance. In response, researchers and practitioners have developed reconfigurable switching chips that are performance-competitive with line-rate fixed function switching chips. These chips provide some programmability through restricted hardware primitives that can be configured with software directives.

This talk will focus on abstractions for programming such chips. The first abstraction, packet transactions, lets programmers express packet processing in an imperative language under the illusion that the switch processes exactly one packet at a time. A compiler then translates this programmer view into a pipelined implementation that processes multiple packets concurrently. The second abstraction, a push-in first-out queue allows programmers to program new scheduling algorithms using a priority queue coupled with a program to compute each packet's priority in the priority queue. Together, these two abstractions allow us to express several packet-processing functions at line rate including in-network congestion control, active queue management, data-plane load balancing, measurement, and packet scheduling.

This talk includes joint work with collaborators at MIT, Barefoot Networks, Cisco Systems, Microsoft Research, Stanford, and the University of Washington.

Anirudh Sivaraman is a graduate student in MIT’s Computer Science and Artificial Intelligence Laboratory. He is broadly interested in computer networking and his recent research work is in the area of programmable forwarding planes.