Princeton University
Computer Science Department

Computer Science 375
Computer Architecture

David August

Fall 2015

Course Description

An introduction to computer architecture and organization. Instruction set design; basic processor implementation techniques; performance measurement; caches and virtual memory; pipelined processor design; RISC architectures; design trade-offs among cost, performance, and complexity.

Announcements

  • REVIEW SESSION: CS Room 105 on January 15, 2016 from 10:30am-12:00pm.
  • Jan 6: Sample Finals are now available.
  • Dec 17: Problem Set 4 is now available.
  • Dec 2: Problem Set 3 is now available.
  • Nov 18: Project 2 [PDF] is now available.
  • Nov 9: Midterms Solutions are now available on Piazza.
  • Oct 21: Sample Midterms are now available.
  • Oct 10: Problem Set 2 is now available. NOW DUE 10/26.
  • Sept 30: Project 1 [PDF] is now available.
  • Sept 21: Problem Set 1 is now available.
  • Sept 19: This is the official web page for COS375/ELE375 Welcome! -DIA

    • Midterm

    The midterm is CLOSED BOOK/CLOSED NOTES, ONE TWO-SIDED HANDWRITTEN SHEET WILL BE ALLOWED.

    Topics include ISA, Assembly Language, Dependences, Calling Convention, Performance (IPC, Amdahl's Law, Bmarks), Arithmetic (Integer, Floating Point), Datapath, Control, Microprogramming.

    Book chapters: Chapters 1-4/B.

    Course Syllabus/Lectures

    All Course Lecture Notes including 1x1, 2x2, and 3x1 formats
    September 16: Introduction Read Chapter 1
    September 21: ISA 1 Read Chapters 1,2, Appendix B
    September 23: ISA 2
    September 28: Metrics
    September 30: Arithmetic Read Chapters 1-3/B, Project partner selection after class,
    October 5: Arithmetic Read Chapters 1-4/B
    October 7:Problem Set 1 due at 5PM
    October 12:RTLRead Chapters 1-4/B
    October 14:
    October 19: Datapath
    October 21: Control
    October 26: MicroprogrammingProblem Set 2 Due at 5PM
    October 26: Q&A, Review 3PM at COS105, small auditorium
    October 28: MIDTERM
    October 31-November 8: FALL BREAK
    November 9:Pipelining Read Chapters 1-4/B
    November 11:Pipeline Control Project #1 Due at 5PM
    November 16: Branch PredictionRead Chapters 1-4/B
    November 18: Branch Prediction
    November 23:Memory HierarchyRead Chapters 1-5/B
    November 24-29:THANKSGIVING BREAK
    November 30:Memory Hierarchy, Virtual Memory
    December 2:Virtual Memory, Memory TechnologyRead Chapters 1-5/B
    December 7:I/O and Disk
    December 9:Instruction-Level ParallelismRead Chapters 1-6/B
    December 14:Multiprocessor Parallelism
    December 16:Multiprocessor Parallelism
    December 17:Problem Set 3 Due at 5PM
    December 18-January 3:WINTER BREAK
    January 6: Problem Set 4 Due at 5PM, late days may be used if really necessary
    January 12:Project #2 Due, no late days may be used
    January 16, 1:30pm:FINAL ExamRoom: Computer Science Building 104

    Supplemental Reading

    Two-Level Branch Prediction A Comparison of Dynamic Branch Predictors that use Two Levels of Branch History by T.-Y. Yeh and Y. Patt
    SMT Simultaneous Multithreading: Maximizing On-Chip Parallelism by Dean M. Tullsen, Susan J. Eggers, and Henry M. Levy
    Cache Coherence A Survey of Cache Coherence Schemes for Multiprocessors by Per Stenstrom
    ILP1 Instruction-Level Parallel Processing: History, Overview and Perspective by B. Rau and J. Fisher
    ILP2 Compiler Technology for Future Microprocessors by W. Hwu, R. Hank, D. Gallagher, S. Mahlke, D. Lavery, G. Haab, J. Gyllenhaal, and D. August
    DRAM A Case for Studying DRAM Issues at the System Level by B. Jacob

    Project References

  • Verilog and FPGA Tutorial
  • The PAW Architecture Reference Manual
  • PAW Binutils Documentation

    • Text

    Computer Organization and Design: The Hardware/Software Interface by David Patterson and John Hennessy. Fifth edition.

    Course Project Information

    Course COS306 COS375 COS475
    Form Factor FPGA FPGA and Real Peripherals Software Simulation
    Difference in Learning Processor Design Simple processor, Datapath and Control Design Pipelined In-Order Processor, Realistic I/O (Keyboard, Monitor, etc) Out-of-Order Processor, Superscalar
    Optional Pipeline Wide Issue, Speculation, Misspeculation Recovery
    ISA LC3 PAW, subset of ARM ’Thumb’ PARC, subset of MIPS32

    Grading

    Project 40%
    Midterm 15%
    Final 25%
    Quizzes EXTRA CREDIT
    Participation 5%
    Homework 15% (best 3 of 4)

    Collaboration Policy

    Assignments should be attempted individually. If you cannot come up with an answer after trying for a while then you may discuss the material or specific issue with a friend/TA/Prof. The answers should be your own. In other words, don't discuss or compare your answers to an assignment with anyone or any source.

    Project teams should work independently. Collaboration among team members is unrestricted (obviously).

    Administrative Information

    Lectures: MW 1330-1450, Room: Robertson Hall 001

    Professor: David August - 221 CS Building - Office Hours: after class or by appointment.

    Undergraduate Coordinator: Colleen Kenny-McGinley - 210 CS Building - 258-1746 ckenny@cs.princeton.edu

    Teaching Assistants:

    Bochao Wang E-Quad C-319B bochaow@princeton.edu Office Hours: Th/F 10:30-11:30AM
    Debajit Bhattacharya E-Quad C-319D dbhattac@princeton.edu Office Hours: T/Th 3-4PM
    Hansen Zhang 241 CS Building hansenz@princeton.edu Office Hours: M/W 3-4PM