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Tyler Sorensen

Postdoctoral Researcher

Princeton University Computer Science

About

I am excited to announce that I will be starting Fall of 2020 at University of California, Santa Cruz (UCSC) as an Assistant Professor in Computer Science!

I am a Post Doc researcher at Princeton University working in Margaret Martonosi’s group. My research interests are in concurrency: programming, modeling, testing, and architecture. In particular, I am interested in exploring new heterogeneous architectures and how programming models can enable development of secure and efficient applications.

I am working on the DECADES project which is funded as part of the software defined hardware (SDH) project.

My previous research focused on GPU programming, namely modeling the semantics of fine-grained thread interactions and using these insights to provide efficient and portable synchronisation idiom implementations.

I received my PhD from the Multicore Programming Group at Imperial College London supervised by Alastair Donaldson. Previously, I worked with Ganesh Gopalakrishnan and Zvonimir Rakamaric at University of Utah.

Interests

  • Concurrency - semantics, testing, verification
  • Heterogeneous Systems - GPUs, accelerators
  • Compilers - portability, optimizations

Education

  • PhD in Computer Science, 2018

    Imperial College London

  • MS in Computer Science, 2014

    University of Utah

  • BSc in Computer Science, 2012

    University of Utah

Publications

Conference

(2019). One size doesn’t fit all: quantifying performance portability of graph applications on GPUs. Best Paper Award in IISWC.

PDF Slides

(2018). GPU schedulers: how fair is fair enough?. in CONCUR.

PDF Slides

(2018). The semantics of transactions and weak memory in x86, Power, ARM, and C++. Best Paper Award in PLDI.

PDF

(2017). Cooperative kernels: GPU multitasking for blocking algorithms. Best Paper Award in FSE.

PDF Code Poster Slides

(2017). Automatically comparing memory consistency models. In POPL.

PDF

(2016). Portable inter-workgroup barrier synchronisation for GPUs. In OOPSLA.

PDF Code Slides

(2015). GPU concurrency: weak behaviours and programming assumptions. In ASPLOS.

PDF Dataset Poster

Publications

Workshop

(2019). Performance evaluation of OpenCL standard support (and beyond). Best Paper Award in IWOCL.

PDF Slides

(2015). I compute, therefore I am (buggy): methodic doubt meets multiprocessors. in TinyToCS (vol 3).

PDF

(2013). Towards shared memory consistency models for GPUs. 1st place undergrad SRC in ICS.

Preprint PDF Poster

Theses

MS: Testing and Exposing Weak GPU Memory Models
BS: Towards Shared Memory Consistency Models for GPUS

Projects


A .gif showing the magnitude of weak memory behaviours for three litmus tests (MP, SB, LB) that appear when stressing individual memory locations of a scratchpad location. These patterns were key in finding and observing weak memory bugs in GPU applications (explained in PLDI’16 paper).



DECADES Tiled Architecture

A new tiled architecture to acclerate a variety of applications

ICL Art of Research

Making art from buggy GPU programs

Online Binary Decision Tree

Simple boolean algebra online tools.

Service

Venue Role Year
PLDI PC 2020
ASPLOS ERC 2020
IWOCL PC 2019
ISCA ERC 2019
ECOOP/ISTA PC for doctoral symp. 2018
PLDI ERC 2018
TinyToCS PC 2016
POPL AEC 2016

Journal reviewer for:

  • ACM TACO
  • Formal Methods in System Design

Awards and Recognition

IISWC'19 Best Paper Award 2019
IWOCL'19 Best Paper Award 2019
PLDI'18 Best Paper Award 2018
FSE'17 Best Paper Award 2017
ICL Art of Research Staff Pick 2016
Outstanding Senior Award (University of Utah) 2014
Snow College 40 under 40 2014
Finalist (top 5) CRA Undergraduate Researcher Competition 2013