This paper describes a very simple mechanism and related compiler support for
software--controlled speculative loads. The compiler issues
speculative load instructions based on anticipated data references and the
ability of the memory system to hide memory latency in high--performance
processors. The architectural support for such a mechanism is simple and
minimal, yet handles faults gracefully. We have simulated the speculative
load mechanism based on a MIPS processor and a detailed memory system. The
results of scientific kernel loops indicate that the speculative load
techniques are effective approaches to hiding memory latency.
- This technical report has been published as
- Software Support for Speculative Loads. Anne Rogers and Kai Li,
ACM Proc. of the 5th Internat. Conference on
Architectural Support for Programming Languages and
Operating Systems, pp. 38-50, 1992.
Links
[1] https://www.cs.princeton.edu/research/techreps/author/454
[2] https://www.cs.princeton.edu/research/techreps/author/318
[3] ftp://ftp.cs.princeton.edu/techreports/1992/372.ps.gz