Paper 1: Improving the Accuracy of Dynamic Branch Prediction Using Branch Correlation

Paper 2: Alternative Implementations of Two-Level Adaptive Branch Prediction

Paper 3: Alternative Implementations of Hybrid Branch Predictors

In paper 1, a dynamic branch prediction ( actually the 2-level branch prediction in paper 2) was introduced by first look through a specific case. Definetely using 2-level adaptive branch prediction is better than a single 2-bit counter predictor. But the case is not very convincing. If initial value of the counter is different and if the input sequence of aa and bb is different, the result could be totally different.

Paper 1 only gave out a 2-level adaptive branch prediction using global branch history. That means we have only a 2-bit shift register for branch history. A better way for branch prediction is described in paper 2.

In paper 2, a far more systematic describtion of 2-level adaptive branch prediction is given out. Three kinds of predictions, GAg, PAg, PAp, are discussed. Of course PAp gives the best prediction result but needs most hardware support.

In paper 3, further research was done based on 2-level branch prediction technology described in paper 2. Hybrid branch prediction uses 2 predictors and mainly discuss the selection mechanisms between the 2 predictors. This kind of prediction is expected to give a better branch prediction and surely uses more hardware.

Currently the branch prediction technology build its prediction accuracy improvement mainly on the cost of using more hardware. Of course it is a good direction since the chip manufacture technique improvment goes fast too. We can build more and more transisters within a single chip. But improvement of branch prediction should also focus on algorithms refinement. Or think about this problem from another angle. Maybe we can do something at the compile stage to make the branch prediction easier? I have no idea till now.