DESIGN EXERCISE #2 -- COS 597A -- FALL 2001

    DUE: 5 PM Friday, December 7

    Design a delay-insensitive, single bit, full adder cell.  Your
    cell will have three dual-rail inputs (two addends and a
    carry-in), and two dual-rail outputs (sum and carry), plus a
    single-rail "done" signal (1 means done and 0 means not done).
    The dual-rail code, you will recall, uses 2 wires for each logical
    data bit: 00 means "idle", 01 and 10 mean zero and one, and 11
    is never used.

    Assume that all three inputs are initially idle, and that they
    will all take on one of the two valid logic codes before any of
    them becomes idle again. Your data outputs must be initially idle,
    and must eventually take on their proper final values without
    making any transitions through any other states, regardless of the
    speed of your gates or your wires, or the different arrival times
    of your inputs, or the possible asymmetry of your gates (e.g.,
    some inputs to an AND gate might propagate more quickly to the
    output than other inputs do). You will therefore need to be
    especially careful with your circuits, perhaps by including extra
    gates to cover timing hazards.
    
    Your "done" signal must become 1 when both sum and carry out are
    valid; after this happens, your data inputs will return to the
    idle code without going through any other states. Your done signal
    must become 0 some time after any input becomes idle.

    You may use all the standard logic gates in your design, plus
    Muller C-elements if you need them.  One approach to this problem
    might be to design separate majority and parity circuits, and then
    combine them to make your adder cell.

    
    DO NOT PUT YOUR NAME ON YOUR PAPER.  Instead, write a secret
    5-digit number known only to you on each page.
    
    You may not collaborate with other students (or with any one else)
    on this assignment, but of course you may ask the instructor any
    questions you like. You may not use papers or books other than the
    ones we've looked at in class (because the answer is out there
    somewhere, for sure). Exception: you may use a logic design
    textbook to review timing hazards if you need to.