Computer Science 471

*Due by 5 PM, Monday Oct. 9, 2000*

The first problem asks you to explore adding the MIPS instruction
`addi` to the single-cycle
implementation of Chapter 5; the next asks the same for
the `jal` instruction.
Problem Set 4 will include exercises
5.15 and 5.17, which are related to the ones
below. You might want to save a copy of your answers.

**1.**
Exercise 5.5 from the Patterson & Hennessy text.
Just use photocopies of the figures if you can't get
the right thing easily
from the Web. When you put your new row in Figure
5.20, please remember that hardware designers really like
don't-care values in logical specifications, since these
often allow smaller, more efficient implementations.
Therefore, please use don't-care (``X'') as much as possible
in your answer to this part of the question.
But please follow the text's idea of the MemRead and MemWrite
signals, which is stricter than what we've done in class, and
which seems to forbid don't-cares on either signal.

**2.** Exercise 5.6 from the text.
Do use Figure 5.29 instead of Figure 5.19. When you
adjust Figure 5.20, show how all the control
lines are
set for `jal`, not just the new ones you may add, and
remember to use don't-cares wherever you can.

**3.** Can you simplify or clean up the PC logic in
Figure 5.29? If the PC is always a multiple of 4, why do
we need the little ``shift left 2'' blobs, and why do we need to
add 4 instead of 1?
Please re-draw all the PC logic (PC, PC+4 adder, Instruction Memory,
the paths that originate in
the instruction itself, the PC displacement adder, and the muxes)
to take advantage of
the fact that PC is always a multiple of 4. Assume the Instruction
Memory does not need
the 2 low-order bits of PC. In your drawing,
be absolutely scrupulous about labelling the widths of the data
paths and showing exactly which bits go where.
If you think this idea won't work, please say why.