Computer Science 471

*Due by 5 PM, Monday Oct. 2, 2000*

**1.**
Problem 4.10 from the Patterson & Hennessy text.

**2.** Problem 4.14 from the text.
(Beware: the address-displacement field of loads and
stores is a *signed*, 2's-complement number.)

**3.** Problem 4.18 from the text.

**4.** Let *x* = 10010.1101
and *y* = 00110011.1 and *z* = -111100.10101
be the sign-and-magnitude
representations in base 2 of three numbers. Show exactly how
*x*, *y*, and *z* would be
represented in the IEEE single-precision floating-point format.
Show *all* the bits, just as they would appear in a MIPS register
or memory word.

**5.** Show the steps involved in the single-precision
floating-point addition of *x* and *y*
from question 4. Use binary operations,
and show all the partial results along the way. The operands must start out in
IEEE format. This question does not ask you to
design any hardware, just to show the computational
steps, like ``shift significand'' and
``normalize'' and ``round'' and things like that. Assume
that the rounding rule is: round to the nearest representable number, and round
to the even one
if the result is exactly half-way between the two nearest numbers.
Show all the bits of the result in IEEE format, just as in
question 4.

**6.** (counts double) Problem 4.52 from the text, with the following
changes.
First, assume that the intermediate terms M15, M14, and so on, have been
properly
shifted and are stored in 32-bit form. Second, in the final paragraph of the
problem statement, change the widths of the adders from 16 bits to 32 bits
(first line and next-to-last line of the final paragraph).

These changes should help you see the structure more clearly, but please be aware that there is no single correct answer to this question. For a tiny tiny amount of extra credit, show how wide each carry-save adder must be.