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for class on Tuesday Sept. 26, 2000
Please read Sections 3.5 through 3.16, skipping 3.12, of the Patterson & Hennessy text, take a look at section A.10 in Appendix A, and be prepared to discuss the following issue:
Pages A-61 through A-64 define the branch instructions used in the MIPS assembler. Some of these are pseudoinstructions that stand for one or more actual instructions. Thus the real MIPS conditional branch instructions do not include all possible conditions. For some (simple) conditions you need to use more than one instruction: a<b, for example, requires a set-less-than instruction (slt) followed by a branch. Note that a full set of comparisons with zero is included. Note also that the condition being tested always involves reading at least one register.
The SPARC architecture (which many of you studied in COS 217) has a different approach to conditional branches. The 217 lecture slides about this are either stapled to this paper, or are available by following this link (postscript). (To appreciate these slides in their proper order, be sure to follow the tiny page numbers in the lower-right corners of the pages.) The architecture includes four condition codes, which are set by variants of the normal arithmetic and logical instructions: addcc and xorcc, for example, are condition-code-setting variants of the add and xor instructions. (Here is roughly what the condition codes mean: N means negative, Z means zero, C means carry out, and V means overflow.) The conditional branch instructions test the condition codes only, and not the contents of the registers.
How would you compare the MIPS and SPARC schemes? Neither is clearly superior, and each has some advantages compared to the other; consider what these might be. To understand the hardware differences, try to do a sketch of the relevant hardware for each machine.