for class on
Dec. 12, 2000
Please read Sections 9.1 through 9.5 of the Patterson & Hennessy text, and be prepared to discuss the following issue:
Multiprocessors that use a single bus to access shared memory need some method to keep their caches consistent or coherent. One protocol for this is illustrated in Figure 9.5 of the text. We will explore the operation of this protocol using several examples. How does it work, anyway? Can you come up with some property or invariant that the protocol should maintain in order to guarantee correct execution?
Course evaluations will be done during the last part of this class.