22
for class on Thursday Dec. 7, 2000
Please re-read the first section of the MIPS R10000 Document Handout (the article by Yeager), paying special attention to the sections on the Branch Unit, the Address Queue, and the Memory Hierarchy. Remember that you are not expected to become an expert on this material. Be prepared to discuss the following:
In this class we will consider the cache and TLB structure of the R10K. How is the out-of-order execution of memory references controlled so that you don't get the wrong answer? What should happen on a TLB miss in the out-of-order context? How about a branch misprediction? Bring your questions!