List of papers pertaining to write buffer design for uniprocessors

B.K. Bray. Specialized caches to improve data access performance. Ph.D. Th., Stanford, May 1993.

T.-F. Chen and J.-L. Baer. Reducing memory latency via non-blocking and prefetching caches. ASPLOS V, pp. 51-61. Oct. 1992.

P.P. Chu and R. Gottipati. Write buffer design for on-chip cache. Int'l Conf. on Computer Design, pp. 311-316, 1994.

S. Dropsho, Real-Time Penalties in RISC Processing. University of Masschusetts-Amherst Department of Computer Science Technical Report TR-95-110, December 12, 1995.

N.P. Jouppi. Cache write policies and performance. ISCA-20, pp. 191-201. May 1993.

D.A. Patterson and J.L. Hennessy. Computer Architecture: A Quantitative Approach, 2nd ed. Ch. 5, "Memory-Hierarchy Design", pp. 373-483. Morgan Kaufmann, 1996.

D.A. Patterson and J.L. Hennessy. Computer Architecture: A Quantitative Approach, 1st ed. Ch. 8, "Memory-Hierarchy Design", pp. 402-497. Morgan Kaufmann, 1990.

L. Schaelicke and A. Davis. Improving I/O performance with a conditional store buffer. MICRO-31, pp. 160-69, Dec. 1998.

K. Skadron and D.W. Clark. Design Issues and Tradeoffs for Write Buffers. HPCA-3, pp. 144-55, Feb. 1997.
Available in postscript or pdf .

K. Skadron and D.W. Clark. Measuring the effects of retirement and load-service policies on write buffer performance. Proceedings of the 1996 Workshop on Performance Analysis and its Impact on Design (PAID), IBM Austin Research Laboratory, Mar. 1996.

A.J. Smith. Characterizing the storage process and its effect on the update of main memory by write through. JACM, 26(1):6-27. Jan 1979.

If you can add any further references on write buffers, please e-mail me at skadron@cs.princeton.edu

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