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application/pdfIEEEIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2018;37;8;10.1109/TCAD.2017.2764482Accelerator architecturesformal verificationmodel checkingsystem-on-chip (SoC)systems modelingTemplate-Based Parameterized Synthesis of Uniform Instruction-Level Abstractions for SoC VerificationPramod SubramanyanBo-Yuan HuangYakir VizelAarti GuptaSharad Malik
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems1692 Aug. 2018837 10.1109/TCAD.2017.27644821705
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