Speaker: Arun Raman, Princeton University
Title: Software Multithreaded Transactional Memory

Abstract:

With the right techniques, multicore architectures may be able to
continue the exponential performance trend that elevated applications
of all types for decades. While scientific programs can often be
parallelized without speculative techniques, speculative parallelism
appears to be the key to continuing this trend for general-purpose
applications.  Recently proposed code parallelization techniques, such
as those by Bridges et al., and by Thies et al., demonstrate scalable
performance on multiple cores by using speculation to divide code into
atomic units (transactions) that span multiple threads in order to
expose data parallelism. Unfortunately, most transactional memory
proposals cannot be used because they only support single-threaded
atomic units. Multithreaded transactions (MTXs) address this problem,
but they require expensive hardware support as currently proposed.
Copy-or-Discard (CorD), proposed by Tian et al., is a software-only
technique, but its utility is restricted by the nonsupport of MTXs, thus
precluding pipelined parallelizations of the kind proposed by
Bridges et al. and Thies et al.

This work proposes a software MTX (SMTX) system that combines the
applicability of hardware MTX with CorD's performance on real
hardware.  SMTX yields a geometric mean speedup of 4.44x on native
hardware with a dual quad-core CMP (8 cores in total) running
speculatively parallelized applications