This paper describes a simple hardware mechanism and related compiler support for software-controlled speculative loads. The compiler issues speculative load instructions based on anticipated data references and the ability of the memory system to hide memory latency in high-performance processors. The architectural support for such a mechanism is simple and minimal, yet handles faults gracefully. We have simulated three speculative load mechanisms based on a MIPS processor and a detailed memory system. The results of scientific kernel loops indicate that speculative load techniques can hide memory latency effectively.