Analysis of Algorithms for the Configuration of Wafer Scale Linear Arrays in the Presence of Defects
Wafer Scale Integration (WSI) is a new technology using Very Large Scale Integration (VLSI). The goal is to implement an entire system in a single silicon wafer containing the equivalent of hundreds of present-day chips. Given the high density and large number of elements in a wafer scale, we expect
some components to be defective due to fabrication errors. Methods are needed to configure the good components into a working system. In this paper we examine four algorithms to connect the good elements in a linear WSI systolic array. We present experimental results obtained by simulation of the
algorithms. We also present an analysis of performance which is applicable to three of the algorithms. The analysis is in term of the number of good elements we expect to utilize.