Published on *Computer Science Department at Princeton University* (http://www.cs.princeton.edu)

Report ID:

TR-093-87

Authors:

Appel, Andrew W. [1]

Date:

April 1987

Pages:

14

Download Formats:

[PDF [2]]

Conventional digital circuit simulators represent circuits using linked data structures, using one or more pointers per connection. To simulate a circuit of N nodes requires space proportional to N log N bits. Many circuits have a hierarchical or repetitive nature, so their specifications can be significantly smaller than the circuits themselves. This paper shows that such circuits can be simulated in space equal to one bit of memory per wire of the circuit, plus space proportional to the (smaller) size of the specification; that is, the space required is only O(N) bits. The algorithm has been implemented; measurements of its efficiency are given.

**Links**

[1] http://www.cs.princeton.edu/research/techreps/author/371

[2] ftp://ftp.cs.princeton.edu/techreports/1987/093.pdf