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for class on Thursday Sept. 30, 1999
Please read Sections 4.1 through 4.5 of the Patterson & Hennessy text, and be prepared to discuss the following issues:
The text develops the design for a MIPS ALU, which is brought to glorious fruition in Figure 4.19. Well, maybe not so glorious: this design is both broken and slow. Please figure out what you might do about these problems. The broken part is the Set output from the most significant bit; to see why, consult Exercise 4.23. Then consider how you would speed up a non-broken version of the ALU. A faster adder will surely help (and is discussed in the text). But even with a fast adder, there will be some long long logical paths through the design. Try to see how to shorten the longest ones by re-arranging, compressing, or otherwise redesigning the logic. Make some sketches of your ideas.