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for class on Thursday Dec. 10, 1998
Please re-read the first section of the MIPS R10000 Document Handout (the article by Yeager), paying special attention to the sections on the Address Queue and the Memory Hierarchy, and be prepared to discuss the following:
In this class we will address issues at the ``back'' end of the R10000 processor, including the cache and TLB structure. How is the out-of-order execution of memory references controlled so that you don't get the wrong answer? What should happen on a TLB miss, and why?