21
for class on Tuesday Dec. 8, 1998
Please re-read Section 6.8 of the text, and then read the first section of the MIPS R10000 Document Handout (the article by Yeager), paying special attention to the sections on Register Mapping and Instruction Queues. Be prepared to discuss the following:
In this class we will try to come to grips with the operation of a processor that can issue multiple instructions simultaneously, and that can execute instructions in an order different from the one the compiler asked for. We will focus on issues involving the ``front'' of the processor such as branch prediction and (especially) register renaming.