COS 591 - Schedule and Readings

Schedule

• 9/22: Routers
• Sanjeev Kumar, Yuanyuan Zhou
• 9/29: Network interfaces
• Dongming Jiang, Cheng Liao, Xiang Yu
• 10/6: Transport protocols and mechanisms
• Regis Colwell, Ben Dressner, Cheng Liao, Xiang Yu
• 10/13: Graphics background
• Yuqun Chen, Regis Colwell, Wagner Correa, Dongming Jiang
• 10/20: Graphics architecture overviews
• Yuqun Chen, Regis Colwell, Minwen Ji
• 11/3: Frame buffers and enhanced memory
• Wagner Correa, Bin Wei, Xiang Yu
• 11/10: Early and sort-middle architectures
• Ben Dressner, Sanjeev Kumar, Hongzhang Shan
• 11/17: Other sort-middle architectures
• Emil Praun, Hongzhang Shan, Bin Wei
• 11/24: Sort-last architectures
• Bin Wei, Yuanyuan Zhou
• 12/1: Sort-first and chuck-rendering architectures
• Yuqun Chen, Minwen Ji, Cheng Liao, Bin Wei
• 12/8: Immersive Displays
• Yuqun Chen, Emil Praun, Yuanyuan Zhou

Tentative Readings

General Readings

• John L. Hennessy and David A. Patterson, "Interconnection Networks", Chapter 7, Computer Architecture: A Quantitative Approach, 2nd Edition, Morgan Kaufmann, 1995.
• Foley, Van Dam, Feiner and Hughes, "Graphics Hardware," Chapter 4, In Computer Graphics Principles and Practice, 2nd Edition, Addison Wesley, 1993.
• S. Molnar and H. Fuchs, "Advanced Raster Graphics Architecture," Chapter 18, in Computer Graphics Principles and Practice by Foley, Van Dam, Feiner and Hughes, 2nd Edition, Addison Wesley, 1993.

System area networking

Routers

• William J. Dally and Charles L. Seitz, "Deadlock-Free Message Routing in Multiprocessor Interconnection Networks," IEEE Transactions on Computers, C-36(5):547-553, May 1987.
• N. Boden, D. Cohen, R.E. Felderman, A.E. Kulawik, C.L. Seitz, J.N. Seizovic, and W. Su, "Myrinet: A Gigabig-per-Second Local Area Network," IEEE MICRO, 15(1):29-36, Feb 1995.
• J. Carbonaro and F. Verhoorn, "Cavallino: The Teraflops Router and NIC," In Proceedings of Hot Interconnects IV, August 1996.
• S. L. Scott and G.M. Thorson, "The Cray T3E Network: Adaptive Routing in a High Performance 3D Torus," In Proceedings of Hot Interconnects IV, August 1996.
• Mike Galles, "Spider: A High-Speed Network Interconnect," IEEE MICRO, 17(1):34-39, 1997.

Network Interfaces

• Matthias A. Blumrich, Kai Li, Richard Alpert, Cezary Dubnicki, Edward W. Felten, and Jonathan Sandberg, "Virtual Memory Mapped Network Interface for the SHRIMP Multicomputer," ISCA, pages 142 - 153, 1994.
• Matthias A. Blumrich, Cezary Dubnicki, Edward W. Felten, and Kai Li, "Protected, User-Level DMA for the SHRIMP Network Interface," HPCA, February 1996.
• Richard B. Gillett, "Memory Channel Network for PCI," IEEE MICRO, 16(1):12-18, Feb 1996.
• G. Buzzard, D. Jacobson, M. Mackey, S. Marovich and J. Wilkes, "An Implementation of the Hamlyn Sender-Managed Interface Architecture," OSDI '96, pages 245-259, October 1996.
• Steve L. Scott, "Synchronization and Communication in the T3E Multiprocessor," ASPLOS-VII, October 1996.

Transport Protocols and Mechanisms

• T. von Eicken, D. Culler, S. Goldstein, and K. Schauser, "Active Messages: A Mechanism for Intergrated Communication and Computation," ISCA, May 1992.
• S. S. Lummetta, A. M. Mainwaring, and D.E. Culler, "Multi-Protocol Active Messages on a Cluster of SMP's," SC97, to appear.
• S. Pakin, V. Karamcheti, and A.A. Chien, "Fast Messages (FM): Efficient, Portable Communication for Workstation Clusters and Massively-Parallel Processors," IEEE Concurrency, 1997, to appear.
• R.P. Martin, A.M. Vahdat, D.E. Culler and T.E. Anderson, "Effects of Communication Latency, Overhead, and Bandwidth in a Cluster Architecture," ISCA, June 1997.
• C. Dubnicki, A. Bilas, K. Li, and J. Philbin, "Design and Implementation of Virtual Memory-Mapped Communication on Myrinet," IPPS, 1997.
• C. Dubnicki, A. Bilas, Y. Chen, S. Damianakis, and K. Li, "VMMC-2: Efficient Support for Reliable, Connection-Oriented Communication," In Proceedings of Hot Interconnects V, 1997.
• B. Chun, A. Mainwaring, S. Schleimer, D. Wilkerson, "System Area Network Mapping," SPAA, pages 116-126, June 1997.

Architectural Support for Graphics

(Thanks to Michael Cox, Adam Finkelstein, Tom Funkhouser for many good suggestions)

Graphics Background

• Alan Watt, 3D Computer Graphics, 2nd edition, Addisop-Wesley, 1993, chapter 5 (Rendering Algorithms, pages 127-158), chapter 7 (Shadows and Textures, pages 237-259), chapter 11 (Anti-aliasing, pages 353-368).
• Alan Watt and Mark Watt, Advanced Animation and Rendering Techniques: Theory and Practice, Addison-Wesley, 1992, chapter 1 (Rendering polygon objects, pages 3-28), chapter 4 (The Theory and Practice of Anti-Aliasing Techniques, pages 111-152).

Graphics Architecture Overview

• Foley, Van Dam, Feiner and Hughes, "Graphics Hardware," Chapter 4, In Computer Graphics Principles and Practice, 2nd Edition, Addison Wesley, 1993.
• S. Molnar and H. Fuchs, "Advanced Raster Graphics Architecture," Chapter 18, in Computer Graphics Principles and Practice by Foley, Van Dam, Feiner and Hughes, 2nd Edition, Addison Wesley, 1993.
• I.E. Sutherland, R.F. Sproull, and R.A. Schumacker, "A Characterization of Ten Hidden Surface Algorithms," ACM Computing Surveys, 6(1):1-55, March 1974.
• N. Chrachorloo, S. Gupta, R.F. Sproull, and I.E. Sutherland, "A Characterization of Ten Rasterization Techniques," SIGGRAPH'89, Computer Graphics, 23(3):355-368, July 1989.
• S. Molnar, M. Cox, D. Ellsworth, and H. Fuchs. "A Sorting Classification of Parallel Rendering," IEEE Computer Graphics and Applications, 14(4), July 1994, 23-32.

Frame Buffers and Enhanced Memory

• F.C. Crow and M.W. Howard, "A Frame Buffer System with Enhanced Functionality," SIGGRAPH'81, Computer Graphics, 15(3):63-69.
• Mary Whitton, "Memory Design for Raster Graphics Displays," IEEE Computer Graphics and Applications, pages 48-65, March 1984.
• Paul Haeberli and Kurt Akeley, "The Accumulation Buffer: Hardware Support for High-Quality Rendering," SIGGRAPH '90, Computer Graphics, 24(4):309-318.
• M. Deering, S. Schlapp, M. Lavelle, "FBRAM: A New Form of Memory Optimized for 3D Graphics," SIGGRAPH '94, Computer Graphics, pages 167-174, 1994.
• W. Donavan, P. Sabella, I. Kabir, and M.M. Hsieh, "Pixel Processing in a Memory Controller," IEEE Computer Graphics and Applications, 15(1):51-61, Jan 1995.
• A. Schilling, G. Knittel, and W. Strasser, "Texram: A Smart Memory for Texturing," IEEE Computer Graphics and Applications, pages 32-41, 1996.
• G. Bishop, H. Fuchs, L. McMillan, E. Scher Zagier, "Frameless Rendering: Double Buffering Considered Harmful, Computer Graphics," pages 175-176, 1994.

Early and Sort-Middle Architectures

• T.H. Meyer and I.E. Sutherland, "On the Design of Display Processors," CACM, 11(6):410-414, June 1968.
• James H. Clark, "The Geometry Engine: A VLSI Geometry System for Graphics," SIGGRAPH '82, Computer Graphics, 16(3):127-132, 1982.
• H. Fuchs and J. Poulton, "Pixel-planes: A VLSI-oriented Design for a Raster Graphics Engine," Proceedings of VLSI Design, 3rd Quarter, 2(3):20-28, 1981.
• J. Poulton, H. Fuchs, J.D. Austin, J.G. Eyles, J. Heinecke, C.H. Hsieh, J. Goldfeather, J.P. Hultquist and S. Spach, "Pixel-planes: Building a VLSI-Based Raster Graphics System," Proceedings of the 1985 Chapel Hill Conference on Very Large Scale Integration, Advanced Research in VLSI, pages 135-60, 1985
• J. Poulton, H. Fuchs, J. Austin, J.G. Eyles, and T. Greer, "Building a 512 x 512 Piexel-planes System," Proceedings of Conference on Advanced Research in VLSI, Stanford University, pages 57-71, March 1987.
• John G. Torborg, "A Parallel Processor Architecture for Graphics Arithmetic Operations," SIGGRAPH '87, Computer Graphics, 21(4):197-204, July 1987.
• B. Apgar, B. Bersack, A. Mammen, "A Display System for the Stellar GS1000," SIGGRAPH' 88, Computer Graphics, 22(4):239-246, 1988.
• J. Eyles, J. Austin, H. Fuchs, T. Greer and J. Poulton, "Pixel-Planes 4: A Summary," In Advances in Computer Graphics Hardware II, pages 183-208, Springer-Verlag, 1988.
• Pixel-Planes 5: A Heterogeneous Multiprocessor Graphics System Using Processor-Enhanced Memories," SIGGRAPH'89, Computer Graphics, 23(3): 79-88, July 1989.

Other Sort-Middle Architectures

• Kurt Akeley and Tom Jermoluk, "High-Performance Polygon Rendering," SIGGRAPH '88, Computer Graphics, 22(4):239-246, 1988.
• Kurt Akeley, "The Silicon Graphics 4D/240GTX superworkstation," IEEE Computer Graphics and Applications, 9(4):71-83, July 1989.
• D. Kirk and D. Voorhies, "The Rendering Architrecture of the DN10000VS," In Proceedings of SIGGRAPH'90, Computer Graphics, 24(4):299-308, 1990.
• M. Deering, S. R. Nelson, "Leo: A System for Cost Effective 3D graphics," SIGGRAPH '93, Computer Graphics, pages 101-108, 1993.
• C. B. Harrell and F. Fouladi, "Graphics Rendering Architecture for a High Performance Desktop Workstation," SIGGRAPH'93, Computer Graphics, pages 93-100, 1993.
• Akeley, Kurt. "RealityEngine Graphics," SIGGRAPH'93, Computer Graphics, 109-116.
• J.S. Montrym, D.R. Baum, D.L. Dignam, and C.J. Migdal, "InfiniteREality: A Real-Time Graphics System," SIGGRAPH'97, Computer Graphics, pages 293-303, August 1997.
• Mark J. Kilgard, "Realizing OpenGL: Two Implementations of One Architecture," Proceedings of the 1997 Siggraph/Eurographics Workshop on Graphics Hardware, Los Angeles, CA, Aug. 3-4, 1997. Pages 45-56.

Sort-Last Architectures

• M. Deering, S. Winner, B. Schediwy, C. Duffy, and N. Hunt, "The Triangle Processor and Normal Vector Shader: A VLSI System for High Performance Graphics," SIGGRAPH '88, Computer Graphics, 22(4):21-30, 1988.
• Molnar, S., J. Eyles, and J. Poulton. "PixelFlow: High-Speed Rendering Using Image Composition," SIGGRAPH '92, Computer Graphics, July 1992, 231-240.
• Steve Molnar, "The PixelFlow Texture and Image Subsystem," In Proceedings of the 10th Eurographics Workshop on Graphics Hardware, Maastricht, The Netherlands, pages 3-13, 1995.
• Gordon Stoll, Bin Wei, Douglas W. Clark, Edward W. Felten, Kai Li, and Patrick Hanrahan, "Evaluating Multi-Port Frame Buffer Designs for a Mesh-Connected Multicomputer," Proceedings of the 22nd ACM/IEEE International Symposium on Computer Architecture, Santa Margherita Ligure, Italy, June 1995, pages 96-105.
• J. Eyles, S. Molnar, J. Poulton, T. Greer, A. Lastra, N. England, and L. Westover, "PixelFlow: The Realization," In the Proceedings of the 1997 Siggraph/Eurographics Workshop on Graphics Hardware, Los Angeles, CA, Aug. 3-4, 1997. Pages 57-68.

Sort-First and Chuck-Rendering Architectures

• M. Kelley, S. Winner, and K. Gould, "A Scaleable Hardware Render Accelerator using a Modified Scanline Algorithm," SIGGRAPH '92, Computer Graphics, 26(2)241-248, July 1992.
• S. Winner, M. Kelley, B. Pease, B. Rivard and A. Yen, "Hardware Accelerated Rendering of Antialiasing Using A Modified A-Buffer Algorithm," SIGGRAPH'97, Computer Graphics, pages 307-316, August 1997.
• Carl Mueller, "The Sort-First Rendering Architecture for High-Performance Graphics," Proceedings 1995 Symposium on Interactive 3D Graphics, 1995, pages 75-84.
• Michael Cox and Narendra Bhandari, "Architectural Implications of Hardware-Accelerated Bucket Rendering on the PC," Proceedings of the 1997 Siggraph/Eurographics Workshop on Graphics Hardware, Los Angeles, CA, Aug. 3-4, 1997. Pages 25-34.
• Matthew Regan and Ronald Pose, "Priority Rendering with a Virtual Reality Address Recalculation Pipeline," SIGGRAPH'94, Computer Graphics, pages 155-162, 1994.
• Jay Torborg and James T. Kajiya, "Talisman: Commodity Realtime 3D Graphics for the PC," In SIGGRAPH'96, Computer Graphics, pages 353-364, 1996.
• Anthony C. Barkans, "High Quality Rendering Using the Talisman Architecture," Proceedings of the 1997 Siggraph/Eurographics Workshop on Graphics Hardware, Los Angeles, CA, Aug. 3-4, 1997. Pages79-88.
• Peter N. Glaskowsky, "Advanced 3D Chips Show Promise," Microprocessor Report,11(8):5-9, June 1997.

Immersive Displays

• C. Cruz-Neira, D.J. Sandin and T.A. DeFanti, "Surround-Screen Projection-Based Virtual Reality: The Design and Implementation of the CAVE," SIGGRAPH'93, Computer Graphics, Auguest 1993, pages 135-142.
• Theo Mayer, "New Options and Considerations for Creating Enhanced Viewing Experiences," Computer Graphics, 31(2):32-34, May 1997.
• David McCutchen, "A Dodecahedral Approach to Immersive Imaging and Display," Computer Graphics, 31(2):35-42, May 1997.
• M. Czemuszenko, D. Pape, D. Sandin, T. DeFanti, G.L. Dawe, M.D. Brown, "The ImmersaDesk and Infinity Wall Projection-Based Virtual Reality Displays," Computer Graphics, 31(2):43-49, May 1997.