Computer Science 471

*Due by 5 PM, Monday Oct. 7, 1996*

The first two problems ask you to explore adding the MIPS instruction
` jal` to the single-cycle
implementation of Chapter 5; the next two ask the same for
the `addiu` instruction.
Problem Set 4 will include exercises
5.3, 5.4, 5.5, 5.13, 5.14, and 5.15, which are related to the ones
below. You might want to save a copy of your answers.

**1.** (5 points)
Exercise 5.1 from the Patterson & Hennessy text.
Make your additions with reference to
Figure 5.29, but be sure to use the *corrected*
version of the figure contained in the handout.
The format of the `jal` instruction
appears in Figure
3.11.

**2.** (5 points) Exercise 5.2 from the text. Show how all the control
lines are
set for `jal`, not just the new ones you add.
Hardware designers really like
don't-care values in logical specifications, since these
often allow smaller, more efficient implementations.
Therefore, please use don't-care (``X'') as much as possible
in your answer.

**3.** (5 points) Exercise 5.11 from the text. MIPS doesn't have a
`subiu` instruction (recall problem number 2 from
Problem Set 2). This may explain why the `addiu`
instruction *sign-extends* the immediate value, just
like `addi`. Sections 4.2 and 4.3 of the text discuss
related matters at length.

**4.** (5 points) Exercise 5.12 from the text. As in problem 2, above,
show how all the control lines are set, and use as many
don't-cares as possible.

**5.** (10 points) Can you simplify or clean up the PC logic in
(the *corrected version* of)
Figure 5.29? If the PC is always a multiple of 4, why do
we need the little ``shift left 2'' blobs, and why do we need to
add 4 instead of 1?
Please re-draw all the PC logic (PC, PC+4 adder, Instruction Memory,
the paths that originate in
the instruction itself, the PC displacement adder, and the muxes)
to take advantage of
the fact that PC is always a multiple of 4. Assume the Instruction
Memory does not need
the 2 low-order bits of PC. In your drawing,
be absolutely scrupulous about labelling the widths of the data
paths and showing exactly which bits go where.
If this idea won't work, please say why.

**6.** (20 points) Problem number 7 (the buggy Pentium problem)
from Problem Set 2 (postponed from
last week due to hardware illness).

**7.** (5 points)
Another chapter questionnaire to help
improve the book before the hardcover printing.
The chapter 4 questionnaire may be found at
http://www.cs.princeton.edu/courses/cs471/chap4.txt.
Please fill it out
and e-mail the result to the publisher as directed.
As usual, please do not
``cc your instructor on this email,'' as the form directs.
To get the 5 points for this question, just write down the time
you sent your message to the publisher.

**8.** (1 point) How long did this take you, not counting the reading,
and with whom did you work?