for class on Thursday Sept. 26, 1996
Please read Sections 4.1 through 4.5 of the Patterson & Hennessy text, and be prepared to discuss the following issues:
1. Let's make a really good ALU for MIPS. How would you incorporate the shift instructions? How would you control the ALU? What's inside the ``Overflow detection'' box in Figure 4.17 and what's wrong with the Set output in the same figure?
2. Suppose the MIPS ALU has a fast, carry-lookahead adder. What might be the slowest path through the ALU, that is, the one with the biggest number of consecutive gate delays? Could you speed up this path, perhaps by using extra hardware?