4

Computer Science 471

*for class on
Tuesday
Sept. 24, 1996*

Please read Sections 3.5 through 3.15 of the Patterson & Hennessy text, take a look at section A.10 in Appendix A, and be prepared to discuss the following issue:

Pages A-58 through A-62 define the branch instructions used in the
MIPS assembler. Some of these are *pseudoinstructions* that stand
for one or more actual instructions. You can tell the real
instructions from the pseudoinstructions because the latter have no
encodings specified. Also, the table of opcodes in Figure A.18
includes the real instructions only.

Thus the real MIPS conditional branch instructions do not include
all possible
conditions. For some (simple) conditions you need to use more than one
instruction: *a<b*, for example, requires a set-less-than
instruction
(`slt`) followed by
a branch. Note that
a full set of comparisons * with zero * is included. Note also that
the condition being tested always involves reading at least one register.

The SPARC architecture (which many of you studied in COS 217)
has a different approach to conditional branches.
Here's where to find the 217
lecture slides about this:
http://www.cs.princeton.edu/courses/cs471/sparc-branches.ps
(it's a Postscript file).
The architecture includes four
* condition codes*, which are set by variants of the normal
arithmetic and
logical instructions: ` addcc` and ` xorcc`, for example,
are condition-code-setting variants of the ` add` and ` xor`
instructions. (Here is roughly what the condition codes mean:
N means negative, Z means zero,
C means carry out, and V means overflow.)
The conditional branch instructions test the condition codes only,
and not the
contents of the registers.

How would you compare the MIPS and SPARC schemes?