for class on Tuesday Nov. 19, 1996
Please read Section 7.3 of the Patterson & Hennessy text, and be prepared to discuss the following issue:
We'll look at the hardware implications of cache associativity and larger block sizes. The text's pictures show one giant memory holding tags and data--does this make sense for big blocks? What logic paths might limit performance in a set-associative cache with big blocks? Remember to think about stores as well as loads as you consider these cache structures.