for class on Thursday Oct. 24, 1996
Please read Sections 6.1 and 6.2 of the Patterson & Hennessy text, and be prepared to discuss the following issues:
1. In the multi-cycle datapath of Chapter 5, some instructions took 5 cycles to execute but some completed earlier. The add instruction, for example, took 4 cycles. The pipelined design of Chapter 6 forces add to take 5 cycles. What do you think about letting instructions finish in the pipeline as quickly as possible (so that, for example, add would write its result one cycle earlier)? Wouldn't this be good for CPI?
2. Can you strengthen and sharpen the authors' somewhat skimpy rationale for pipeline registers (pp. 426-7)? What exactly are they for? And why is the PC shown in the figures of this chapter as a squat little register, while the interstage registers like IF/ID are tall and elegant? The authors mean something by this distinction (see the Elaboration on p. 436)--do you agree with them?