9
for class on
Monday
Oct. 15, 2012
Please read Sections 4.4 and D.2 (on the CD and also here) of the Patterson & Hennessy text.
The control for the single-cycle MIPS datapath involves mapping bits
from the opcode (always) and bits from the function field (sometimes)
into control signals for the various multiplexors, the ALU, the memory,
etc. The text presents this design in bits and pieces, focusing first
on the control of the integer ALU, and then moving on to the other
control signals. In this class we will try to integrate this control logic into something a little
more regular and flexible.
Please turn in written responses to these questions:
1. First, use the text's scheme directly. On a copy of Figure 4.24 please write all the values of all the control signals (the blue wires) required to execute the addi (add immediate) instruction. Remember that the inputs and outputs of the ALU control blob have multiple bits, and tell us what they all should be for this instruction.
2. If you attempted to do the same for the andi (and immediate) instruction, you would fail. Why?
Then, be prepared to discuss the following in class:
3. During this class we will explore the text's control design and extend it to cover some instructions not in the subset used in this chapter. If you look closely at the text's scheme you will quickly see that it fails for many non-subset (and non-floating point) instructions, including andi, which you looked at above. Think about how this control design might be unified into some single coherent structure that could be naturally extended to include the rest of the instructions. You should look at Section B.10, and especially Figure B.10.2, as part of your preparation, and of course sketches of your hardware ideas will be helpful. Please avoid trickery such as doing arithmetic on the opcode! We're in search of a simple, extensible structure.