21
for class on
Monday
Dec. 10, 2012
Please read Section 5.8 of the text, and pages 5.9-10 through 5.9-16 from the CD (here is a copy of section 5.9 if you need it). The individual processors in the Intel and AMD multicore chips discussed in Section 5.10 have private writeback L1 and L2 caches, but share a single L3 cache. The processors or cores share a physical address space and thus appear to run the risk that their store instructions might sometimes conflict with each other, leading to potential inconsistencies in the private caches. The chips, of course, have mechanisms to deal with this.
Please turn in a written response to this question:
1. Threads or processes can be synchronized by using semaphores. The Chief Software Architect of your lavishly-funded startup company (a Harvard graduate, let's say) has invented a “packed semaphore” datatype in which all of an application's semaphores are placed in a block of contiguous addresses. Should the software architect get a bonus or be fired? Please answer in the context of a multicore processor (such as those in the reading), pointing out, at about the two-paragraph level of detail, either why this is a great idea or why it might lead to problems.
Then, be prepared to discuss the following in class:
2. One cache coherence protocol is illustrated in Figures 5.9.9, 5.9.10, and 5.9.11 of the text. This protocol uses just three states: Invalid, Shared (read only), and Exclusive (read/write). We will add a fourth state and, confusingly, recycle one of the names from the three-state FSM (sorry about that). Our new states will be Invalid, Shared (read only), Exclusive (but not dirty), and Modified (dirty). We will develop state diagrams in the style of Figure 5.9.10. The caption of Figure 5.9.9 briefly discusses this “MESI” protocol. You should make a sketch of your state-diagram ideas as part of your preparation.