2
for class on
Wednesday
Sept. 19, 2012
Please read or perhaps re-read sections C.1, C.2, C.3, C.7, and C.8 of
Appendix C of the Patterson & Hennessy text (it's on the CD, and also here). You can ignore the Verilog material.
Please turn in written responses to these questions:
1. Make gates out of muxes. Show how to use a single 2-input multiplexor to implement AND, OR, NOT, and EXOR gates (i.e., one mux per gate), if you can. Assume that logical values 0 and 1 are available, and that your two inputs are presented in high-true form only. One of these gates should give you trouble; please explain.
2. What hardware would you use to test 32-bit quantities for equality? Draw a gate-level circuit with 32-bit inputs x and y, and 1-bit output x==y. Use some clear shorthand for repeated instances of the same structure. Gates with lots of inputs are OK with us.
3. What hardware would you use to test whether one 32-bit quantity is strictly less than another? Sketch the general idea for a combinational logic circuit that would take 32-bit, signed, 2's-complement, integer inputs x and y and produce a 1-bit output x<y. You do not need to draw all the gates; just be clear about what you intend. Include an adder if you like.
4. Compare the sizes and speeds (the worst-case sum of the delays through the gates--never mind the wires) of the circuits you proposed for questions 2 and 3: which is faster, and why? How does the speed of the circuits depend on the width of the operands?
5. Draw a gate-level circuit for
x>=0 (where x is
32-bit, signed, etc., etc.).
Then, be prepared to discuss the following topics in class:
6. We looked at the datapath of a simple processor last time. Let's add the nasty details: the control and the clocking. Assume that all the state devices (accumulator, registers) are made of rising-edge-triggered D-type flip-flops (like Figure C.8.4, but with rising edge), and that the Memory is written by a pulse rather than a clock-edge. Try to figure out exactly when each state device should be clocked, when each multiplexor should be switched, and when the Memory should be written. You will want to do a sketch of your ideas about this. You may assume the existence of any number of (periodic) clock signals of whatever shape you like. You need not concern yourself with clock skew, races, or other electronic esoterica.
7. We want this machine to get the right answer, of course, but we also want to get the answer fast. How would you analyze the speed of our simple processor?