Computer Science/Electrical Engineering 375:
Computer Architecture and Organization
Course Information--Fall 2010
Course Description
This course is an introduction to computer architecture and organization,
with a special focus on the basic principles underlying contemporary, mainstream,
microprocessor processor design. It will explore the interaction of hardware and software,
and consider the efficient use of hardware to achieve high performance.
Topics will include the MIPS instruction-set architecture, computer arithmetic,
processor design, performance measurement and analysis, pipelining, caches
and virtual memory, input/output, and design tradeoffs among cost, performance,
and complexity.
Administrative matters
Instructor
Douglas Clark
309 C.S. Building, 258-6314
doug@princeton.edu
Office hours: send email for an appointment
Teaching Assistant
Feng Liu
223 C.S. Building
fengliu@princeton.edu
Office hours: M 11-12 and Th 4:30 - 5:30. Or send email for an appointment.
When and where
Mondays and Wednesdays, 1:30--2:50, 105 Bobst Hall
Prerequisites
Prerequisites for this course are COS 217, Introduction to Programming
Systems, and ELE 206/COS 306, Introduction to Logic Design.
Requirements
Class participation
This course will use a discussion, not lecture, format. Each class will cover
particular subjects from the assigned reading. Students will be expected to have carefully read
the relevant assigned readings and to have prepared responses to, and analyses
of, any assigned discussion questions or topics. The quality and quantity
of student participation in class discussions is worth one-third of the
course grade. Participation grades will reflect the quality of the
student's analysis as well as the student's contribution to the process
of discussion: making connections with other students' remarks, raising
overlooked issues, asking good questions, making good summaries. Note that
effective participation requires a great deal more listening than
speaking, and in particular requires careful listening to other students, and not only to the instructor.
Mini (but many) problem sets
Part of the student's preparation for each class will involve short written responses
to assigned questions on that day's reading; these will sometimes include exercises from the text.
These mini-problem sets will together be worth one-ninth of the course grade. Written homework will be due no later
than the beginning of the class to which it pertains, and no credit will be given
for late papers unless there are extraordinary circumstances and/or prior
arrangements. Hand-drawn pictures and hand-written text are perfectly fine, as long as they
are dark, large, and clear.
Examinations
An open-book midterm examination will be given on Wednesday, Oct. 27. It will cover material presented and discussed in the
classes and assigned reading through Monday, Oct. 25. It will be worth
one-ninth of the course grade.
An open-book final examination will be given during the fall-term final
exam period. It will cover all of the assigned readings and material presented
and discussed in class. It will be worth two-ninths of the course grade.
Design Project
A final project, due just before Dean's Date, will involve building a cycle-accurate simulation model of a simple processor. Students will work in pairs or threes on the project, which will be worth two-ninths of the course grade. (Groups of three will have a slightly larger assignment.) More information on the project will appear as the semester develops.
Here are materials for the final design project:
Reading
Textbook
David Patterson and John Hennessy,
Computer
Organization and Design: The Hardware/Software Interface, 4th
edition, Morgan Kaufmann Publishers or possibly Elsevier, 2009 definitely.
Other readings
Copies of any supplemental readings will either be handed out in class or linked to on the course website.
Schedule
Introduction: Sept. 20
-
Topics: Introduction to the course; design of a simple processor
-
Reading: Patterson and Hennessy text, chapter 1
Review of Logic Design: Sept. 22
-
Topics: Combinational logic; state elements; clocks and timing;
memory elements; finite-state machines
-
Reading: Patterson & Hennessy, Appendix C
The MIPS Instruction-Set Architecture:
Sept. 27, 29, Oct. 4
-
Topics: Introduction to MIPS architecture; encoding/representation
of instructions; memory addressing issues; branching
-
Reading: Patt. & Henn., chapter 2
Arithmetic for Computers: Oct. 6, 11
-
Topics: Integer and logical operations; constructing a simple MIPS
ALU; floating point operations
-
Reading: P & H, chapter 3
MIPS Processor Design: Oct. 13,
18, 20
-
Topics: MIPS datapath; implementing control; single-cycle processor
design; multiple-cycle processor design; microprogramming; exceptions
-
Reading: P & H, chapter 4 (early sections)
Processor Performance: Oct. 25
-
Topics: defining and measuring computer performance; bad and good
metrics; benchmarks; Amdahl's Law; the Iron Law
-
Reading: P & H, parts of chapter 1
MIDTERM examination: Wednesday Oct. 27 (in class)
Fall recess
Pipelining: Nov. 8, 10, 15, 17, 22
-
Topics: the idea of pipelining; pipelined MIPS datapath; pipeline
control; hazards; stalls and bypassing; exceptions; performance of pipelined
systems
-
Reading: P & H, chapter 4 (later sections)
Thanksgiving recess
Memory Hierarchy: Nov. 29, Dec. 1, 6, 8
-
Topics: Caches and locality; virtual memory; translation lookaside
buffers; protection and page faults; performance tradeoffs in cache and
TLB design
-
Reading: P & H, chapter 5
Reading: Handout
Parallel Potpurri: Dec. 13, 15
-
Topics: cache coherence; out-of-order execution; multicore; future possibilities
-
Reading: P & H, chapter 7
DESIGN PROJECT due Monday, January 10
FINAL examination given during exam period
Doug Clark, 9/15/10