6
for class on
Wednesday
Oct. 6, 2010
Please read sections 3.1, 3.2, C.5, and C.6 (skipping the Verilog parts) of the Patterson & Hennessy text.
Please turn in written responses to these questions:
0. Who is or are your partner(s) for the final design project?
1. Find the shortest sequence of MIPS instructions to determine the absolute value of a 2's complement integer. In other words, produce the actual code for the MIPS psuedoinstruction
abs rdest, rsrc
Hint: three instructions are all you need.
2. Exercise C.24 from the text. A copy of Figure C.5.10 is here.
3. Exercise C.25 from the text, but for "Figure 3.5 on page 232" substitute "Figure 3.2 on page 226."
Then, be prepared to discuss the following in class:
4. The text develops the design for a MIPS ALU, which is brought to glorious fruition in Figure C.5.12. Well, maybe not so glorious: this design is both broken and slow. Please figure out what you might do about these problems. As you explored in the exercises above, the broken part is the Set output from the most significant bit. Consider how you might speed up a non-broken version of the ALU. A faster adder will surely help (and is discussed in the Appendix text). But even with a fast adder, there will be some long combinational logic paths through the design. (Remember that a logical "path" is just a route from some input to some output that passes through a sequence of interconnected parts and that is actually used by some instruction.) Try to see how to shorten the longest ones by re-arranging, compressing, or otherwise redesigning the logic. Feel free to use more logic to reduce delays: transistors are cheap, and nanoseconds are precious. Make some sketches of your ideas.