4
for class on
Wednesday
Sept. 29, 2010
Please read sections 2.7 through 2.9, along with 2.17 of the Patterson & Hennessy text. Pages B-59 through B-63 define the branch instructions used in the MIPS assembler. Some of these are pseudoinstructions that stand for one or more actual instructions.
If you need to, please also refresh your knowledge of conditional branches in the x86 (or IA-32). Use any resources you like, including the manuals linked to at the bottom of the cos 217 homepage. This architecture uses status flags (also known, and in truth more commonly known, as condition codes). A conditional branch is accomplished by testing various combinations of the condition codes in the Jcc instruction, rather than examining registers directly, as in MIPS.
Please turn in written responses to these questions:
1. Exercise 2.18.2 for row a of the table.
2. Exercise 2.18.2 for row b of the table.
3. Assuming that integers x and y are in registers, what actual MIPS instruction(s) (i.e., not pseudoinstructions) would you need to branch if x < y ?
4. Same question for IA-32 (a.k.a. x86).
Then, be prepared to discuss the following in class:
5. How would you compare the MIPS and IA-32 schemes? Do you see either as clearly superior, or do you think that each has some advantages compared to the other? What might these be? To understand the architectural differences, write out corresponding code for branching on conditions other than the plain less-than of questions 3 and 4 above, e.g., less-than-zero, not-equal, etc. To understand the hardware differences, try to do a sketch of the relevant hardware for each machine.