22
for class on
Wednesday
Dec. 15, 2010
Please read Sections 4.10 and 4.11 of the text.
Please turn in anonymous written responses to these course-evaluation questions:
1. What aspects or elements of the course worked well for you?
2. What aspects or elements of the course did not work so well for you? Can you suggest improvements in the course for future years?
Then, be prepared to discuss the following in class:
3. We will try to do a casual and high-level design of an out-of-order MIPS processor. Imagine the following hardware: in-order decoding of four instructions per cycle; register re-naming (every instruction that writes a MIPS register gets allocated a physical register from a multi-ported pool of unused registers, and subsequent readers of that register--before the next write--read that physical register); multiple functional units (like ALU's and floating-point multipliers and such); a multi-ported cache that can handle a small number of simultaneous hits and misses; a really excellent branch predictor; hardware to check load and store addresses to avoid conflicts; an in-order graduation unit that allows up to four consecutive instructions to graduate, or commit, each cycle; and a 64-entry re-order buffer to hold instructions between decode and graduation.
Between in-order decode and in-order graduation, instructions execute as soon as their operands are ready (not counting branches), and the necessary functional units are available. No permanent architectural state changes are made, however, until an instruction graduates (without having caused any exceptions).
We will focus especially on register renaming (what hardware should we use, in addition to the physical register file? and how could we recycle physical registers?), branch misprediction (how can we "unwind" instructions mistakenly executed? and when?), and, of course, exceptions.