20
for class on
Wednesday
Dec. 8, 2010
Please read sections 5.10, 5.11, and 5.12 of the text.
You have a project milestone due Friday, so no written assignment today.
But nevertheless please do be prepared to discuss the following in class:
Consider the data reference of an unlucky (but legal) load word instruction.
How many bad things can happen to it?
Missing in the cache is certainly one such thing, as is missing in the TLB.
What about the memory reference made by the TLB miss routine to access the
Page Table--can it too miss here and there? We will analyze a single load-word instruction
whose data reference encounters every possible non-fatal problem the
memory system can put in its way, and yet still manages to complete. The fine print: the address is properly aligned; Process page tables reside in the System virtual address space and the System page table lives in un-mapped physical memory (see Elaboration point 5 on page 501); page faults are handled as discussed on pp. 512-514 of the text.
Please think about what all the problems might be and how each one is resolved. You should probably write a list of the problems as part of your preparation.