16
for class on
Monday
Nov. 22, 2010
Please read Sections 5.1 and 5.2 of the text.
Please turn in a written response to these questions:
For both of these, answer for both rows a and b of the table in Exercise 5.4. In some printings there's an obvious typo in the Index column for row b.
1. Exercise 5.4.4
2. Exercise 5.4.5
Then, be prepared to discuss the following in class:
3. There are really three different types of cache references: loads, stores, and instruction (or "I-stream") reads. Each can either hit or miss in a cache. We'll look at basic cache hardware and go through some simple cache scenarios involving these reference types. Cache misses ordinarily cause instructions to wait; how might the processor pipeline accomodate each of the three possible sources of cache misses?