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for class on Thursday Nov. 16, 2000
Please read Sections 7.1 and 7.2 of the Patterson & Hennessy text, and be prepared to discuss the following issue:
There are really three different types of cache references: loads, stores, and instruction (or "I-stream") reads. Each can either hit or miss in a cache. We'll look at basic cache hardware and go through some simple cache scenarios involving these reference types. Cache misses ordinarily cause instructions to wait; how might the processor pipeline accomodate each of the three possible sources of cache misses?